In electronic circuits voltage generator circuits are utilized to provide supply and reference voltages required for operation of the circuits. For example in a conventional dynamic random access memory ("DRAM"), a bias and equilibration voltage generator circuit generates a voltage V.sub.cc /2 used for biasing and equilibrating digit lines and for supplying a reference voltage to one plate of a storage capacitor contained in each memory cell, as known in the art. FIG. 1 is a schematic of a conventional bias and equilibration voltage generator circuit 10 utilized in a conventional DRAM to generate the bias and equilibratlon voltage V.sub.cc /2. The voltage generator circuit 10 includes a PMOS feedback transistor 12 which presents a variable resistance between a supply voltage V.sub.cc and a first bias node 14 in response to an output voltage on an output node 26 applied to its gate.
The voltage generator circuit 10 further includes a bias circuit 15 comprising an NMOS diode-coupled transistor 16 coupled between the first bias node 14 and a tracking node 17, and a PMOS diode-coupled transistor IS coupled between the tracking node 17 and a second bias node 20. As understood by one skilled in the art each diode-coupled transistor 16 and 18 has its gate coupled to its drain and exhibits a current-voltage relationship that approximates a diode having a threshold voltage equal to the threshold voltage of the transistor. The threshold voltages of the diode-coupled transistors 16 and 18 are designated as V.sub.tn1 and V.sub.tp1, respectively. In operation the diode-coupled transistors 16 and 18 maintain a voltage differential between the first and second bias nodes 14 and 20 of approximately V.sub.tn1 +V.sub.tp1. Note that the diode-coupled transistor 18 has its back-bias terminal coupled to its source in order to minimize its threshold voltage V.sub.tp1, as will be explained in more detail below. An NMOS feedback transistor 22 presents a variable resistance between the second bias node 20 and ground, or another suitable reference voltage, in response to the voltage on the output node 26 applied to its gate.
The voltage generator circuit 10 further includes an NMOS drive transistor 24 presenting a variable resistance between the supply voltage V.sub.cc and the output node 26 in response to the voltage on the first bias node 14 applied to its gate, and a PMOS drive transistor 28 presenting a variable resistance between the output node 26 and ground in response to the voltage on the second bias node 20 applied to its gate. The driver transistors 24 and 28 are typically formed having larger current driving capacities than the transistors 12. 16. 18. and 22 to provide sufficient current for driving loads coupled to the output node 26. In addition, such large current driving capacity enables the transistors 24 and 28 to quickly return the voltage on the output node 26 to the desired output voltage in response to load variations. The larger current driving capacity of the transistors 24 and 28 may be achieved for example by increasing the respective channel widths of the transistors.
The transistors 16, 18. 24, and 28 have threshold voltages V.sub.tn1, V.sub.tp1, V.sub.tn2, and V.sub.tp2, as shown in FIG. 1. These threshold voltages determine the value of the output voltage developed by the generator circuit 10 on output node 26. In the bias and equilibration circuit 10, the desired output voltage on the node 26 is V.sub.cc /2, and the respective threshold voltages are selected accordingly. In addition the threshold voltages ideally have values which ensure the NMiOS drive transistor 24 and PMOS drive transistor 28 do not simultaneously present relatively low resistances between their respective sources and drains. If both the drive transistors 24 and 28 simultaneously present low resistances, a large current may flow from the supply voltage V.sub.cc through the transistors 24 and 28 to ground causing the voltage generator circuit 10 to dissipate a large amount of power. No such current path is present as long as the transistors 24 and 28 do not simultaneously present low resistances. To ensure the drive transistors 24 and 28 do not simultaneously present low resistances, the diode-coupled transistors 16 and 18 and driver transistors 24 and 28 are formed such that the summation of the threshold voltages of the diode-coupled transistors 16 and 18 is less than the summation of the threshold voltages of the drive transistors 24 and 28: V.sub.tn1 +V.sub.tp1 &lt;V.sub.tn2 +V.sub.tp2. One skilled in the art will realize a finite current may flow through the drive transistors 24 and 28 even when the threshold voltages satisfy the desired relationship but when the threshold voltages are so selected the power dissipated due to such finite current is typically negligible.
In operation of the voltage generator circuit 10, under quiescent operating conditions the output voltage on node 26 equals V.sub.cc /2, causing the feedback transistors 12 and 22 to drive the control nodes 14 and 20 to respective bias voltages. For the circuit 10, the tracking node 17 is at approximately the voltage V.sub.cc /2 so the bias voltages on nodes 14 and 20 are approximately V.sub.cc /2+V.sub.tn1 and V.sub.cc /2-V.sub.tp1, respectively. Under these quiescent conditions, both drive transistors 24 and 28 present relatively high resistances. When external circuitry (not shown in FIG. 1) loads the output node 26 the output voltage on node 26 deviates from the desired output voltage V.sub.cc /2. Two things occur when the output voltage on node 26 does lower than the desired value V.sub.cc /2 by a predetermined amount. First, the feedback transistor 12 drives the voltage on the first bias node 14 toward the supply voltage V.sub.cc in response to the decreasing voltage on node 26. Second, in response to the increasing voltage on the first bias node 14, the NMOS drive transistor 24 drives the voltage on the output node 26 toward the supply voltage V.sub.cc. As the NMOS drive transistor 24 drives the output voltage on node 26 toward the voltage V.sub.cc and thereby back to the desired output voltage V.sub.cc /2, the feedback transistor 12 drives the voltage on the first bias node 14 back to the bias voltage until the quiescent operating condition is once again established.
When the output voltage on node 26 increases above the desired output voltage V.sub.cc /2, the feedback transistor 22 and drive transistor 28 operate similar to transistors 12 and 24 to restore the desired output voltage. First, the feedback transistor 22 drives the voltage on the second bias node 20 toward ground in response to the increasing voltage on node 26. Second, in response to the decreasing voltage on the second control node 20, the PMOS drive transistor 28 drives the voltage on the output node 26 toward ground. As the PMOS drive transistor 28 drives the output voltage on node 26 toward ground and thereby back to the desired output voltage V.sub.cc /2, the feedback transistor 22 drives the voltage on the second bias node 20 back to the bias voltage until the quiescent operating condition is again established.
As previously discussed, proper operation of the voltage generator circuit 10 requires the diode-coupled transistors 16 and 18 be formed having respective threshold voltages satisfying the relationship V.sub.tn1 +V.sub.tp1 &lt;V.sub.tn2 +V.sub.tp2, which may be difficult to do. The threshold voltages of the diode-coupled transistors 16 and 18 may be reduced in a variety of ways, including varying the channel width of the transistors, and varying the doping concentration in various regions of the transistors. Reducing the threshold voltages of the diode-coupled transistors 16 and 18 through either of these methods, however, may result in undesirable additional process steps when forming the voltage generator circuit 10. Another method of reducing the threshold voltage of a MOS transistor is utilizing the "body effect" of the transistor by coupling the back-bias voltage terminal of the transistor to its source. The body effect of a MOS transistor is the variation in the threshold voltage of the transistor as a function of the voltage across the source-substrate junction of the transistor. As understood by those skilled in the art, the threshold voltage of a NIOS transistor increases as the source-substrate voltage increases and decreases as the source-substrate voltage decreases.
In the circuit 10, the body effect of the transistor 18 is utilized to lower its threshold voltage V.sub.tp1 by coupling its back-bias terminal to its source such that the source-substrate voltage of the transistor is approximately zero. It should be noted that typically the back-bias voltage terminal of both the diode-coupled transistors 16 and 18 may not be simultaneously coupled to their respective sources because the threshold voltages of other transistors formed in the semiconductor substrate containing the voltage generator circuit 10 may be undesirably affected. Typically, one of the diode-coupled transistors 16 and 18 is formed in a well region, and it is this transistor whose back-bias voltage terminal is coupled to its source. In the embodiment of FIG. 1. the voltage generator circuit 10 is formed in a p-type semiconductor substrate with the diode-coupled transistor 16 formed in the substrate and the diode-coupled transistor 18 formed in an n-well region. Thus, the back-bias voltage terminal of the transistor 18 is coupled to its source while the back-bias voltage terminal of the transistor 16 is typically coupled to a negative voltage source, such as a -1.2 volt substrate pump circuit, or to ground. In this configuration, the transistor 18 has the threshold voltage V.sub.tp1 corresponding to a zero source-substrate voltage and the transistor 16 has the threshold voltage V.sub.tn1 corresponding to the voltage on the node 17 (approximately V.sub.cc /2 under quiescent operating conditions). The voltage on the node 17 increases the threshold voltage V.sub.tn1 relative to the value for zero source substrate voltage, which makes it more difficult to ensure V.sub.tn1 +V.sub.tp1 is less than V.sub.tn2 +V.sub.tp2 as desired.
There is a need for a voltage generator circuit including two series connected diode-coupled transistors having reduced threshold voltages to ensure low power operation of the voltage generator circuit.